Field of the Invention
The present invention relates to an arrangement for testing integrated circuits provided in a wafer.
Description of the Background Art
A semiconductor wafer testing system is known from DE 103 42 312 A1, which corresponds to U.S. Pat. No. 6,888,365. Integrated circuits generally begin their manufacturing process in the form of a semiconductor die or integrated circuit, chip or “die” on a flat, circular wafer, which is called a substrate or semiconductor substrate. The semiconductor die usually comprises a rectangular part of the wafer surface and is also known under the designation of integrated circuit, chip, circuit or the like. Each wafer is usually segmented by scribe or saw lines into multiple semiconductor dice, which generally form essentially identical, rectangular structures of integrated circuits. Some semiconductor dice may be design or test semiconductor dice. Other semiconductor dice may be edge semiconductor dice, in which the wafer does not permit the formation of a complete semiconductor die along the edge of the wafer. A slotted region or scribe line is situated between the semiconductor dice on wafers. The size of the scribe line varies with the number and arrangement of semiconductor dice on the wafer. Once the manufacture of the integrated circuit has been completed, the wafer is, e.g., scribed and broken or cut along the scribe line to separate the semiconductor dice for use in component packages. Integrated circuits of the semiconductor dice are tested after manufacturing to ascertain whether a suitable integrated circuit was produced. The integrated circuits may be tested individually after the wafer has been separated. Moreover, the integrated circuits may be measured with the aid of a multi-side testing device before the wafer is separated. A testing of the integrated circuits generally includes the use of mechanical probes of a test apparatus. The mechanical probes are also referred to as probe cards, according to their shape. The mechanical probes contact test terminal areas on the integrated circuit. After the electrical contacting, the test apparatus applies input signals or voltages to the integrated circuit and subsequently receives output signals or voltages from the integrated circuit. The test instrument may have the same number of data testing channels as the number of data terminal areas of the integrated circuit. If an integrated circuit has, for example, eight data terminal areas, for example eight data test channels are connected to the eight test terminal areas on the integrated circuit for reading and writing data.
In addition to the circuit parts and contacts for performing its actual function, an integrated circuit often contains additional circuit parts which are required only once during manufacturing for testing the actual functions. An integrated circuit usually requires a separate interface for providing the test instrument with access. Via this test interface, the circuit is configured for the individual tests, the circuit blocks to be tested are stimulated, and their responses are transmitted to the external test instrument. The integrated circuits may be tested twice during the course of the manufacturing process. The first time, a test takes place after a wafer, which contains multiple integrated circuits of the same type, was manufactured. This test is called the wafer level test. The second time, the integrated circuits are tested after they have been separated and packaged. This test step is also referred to as the final test.
In other test systems, integrated circuits are connected in parallel on the wafer. Each integrated circuit has separate data terminal areas for testing different sections or regions of the integrated circuit. Data terminal areas for similar sections or regions of each integrated circuit are connected, for example, to a wafer test terminal area via a bus or another routing mechanism. DE 103 42 312 A1 also relates to a parallel testing of integrated circuits which are provided in a semiconductor wafer. The semiconductor wafer testing system in DE 103 42 312 A1 tests one or multiple semiconductor die clusters on a semiconductor wafer. A test circuit is used to test multiple sections or regions of each semiconductor die in parallel. The semiconductor wafer testing system has a buffer which is connected to the semiconductor die cluster via the test circuit. The buffer writes test data to one section of each semiconductor die in the semiconductor die cluster. The buffer reads test data from the section of each semiconductor die in the semiconductor die cluster.
An arrangement for testing chips produced from a wafer is known from DE 198 31 563 A1, which corresponds to U.S. Pat. No. 6,366,110, and in which test signals are fed to the chips with the aid of a test head. The test signal may be applied serially or in parallel to the chips in the wafer with the aid of test lines provided in a saw edge of the chips. The saw edge may also be referred to as a kerf or scribe line. Logic units for data compression may be provided in the saw edge.
WO 03/085563, which corresponds to US 2002/0157082, provides for a number of narrow metal paths in the scribe line for the connection between integrated circuits on a wafer. These metal paths are typical less than 0.1 mm long and typically only a few μm wide. These narrow metal paths generate short circuits with only a slight probability during the process of scribing the wafer.